Trends in Test part three – IP to the pin
12 July 2011
In this four-part series, National Instruments details key technologies and methodologies impacting the test and measurement industry in 2011. This penultimate instalment discusses the concept of IP-to-the-pin and how it can help the electronics industry save time and money by facilitating concurrent design and test.
Engineers around the globe are starting to realise an unfortunate truth: over the past decade many companies have chosen to invest more in their design tools than their test engineering tools.
Consequently, test engineers often find themselves lacking the required tools to fully validate the latest software-centric electronic devices.
Pundits in every major industry have proposed solutions to bridge this gap. In the semiconductor industry, experts have recommended the solution of protocol-aware test; visionaries in defence have proposed synthetic/virtual instrumentation; and the automotive industry has adopted hardware-in-the-loop and model-in-the-loop test.
Although all of these instrumentation architectures appear distinctive, a closer look reveals certain commonalties: a system-level approach, the integration of design and test concepts, and the potential to extend software architectures into FPGAs.
The next phase in integrating design and test is the ability for engineers to deploy design building blocks, known as intellectual property (IP) cores, to both the device-under-test (DUT) and the reconfigurable instrument.
For instance, consider a multiple-input, multiple-output (MIMO) system on a chip that includes receivers, transmitters, converters, filters and a processor. In addition, this SOC features software IP such as modulation, encryption and communication protocols.
To fully validate the highly integrated hardware and software of the SOC, test systems must emulate another communication device in the system, such as a base station. This presents an ideal case for concurrent design and test, because the SOC and the test system share common IP blocks.
This approach of directly embedding SOC design IP into test instrumentation is known as IP-to-the-pin, because it drives user-defined software close to the I/O pins of the test instruments. Pushing design IP into instrumentation hardware can simultaneously shorten test development and improve test coverage.
There are two key trends that are simplifying the industry shift to IP-to-the-pin capability: the proliferation of field-programmable gate arrays and the availability of high-level software to program them.
Vendors are integrating FPGAs within next-generation instrumentation in order to improve performance and maximise user-configurability. Moore’s Law has accelerated this adoption of FPGA technology by rendering the cost and size of programmable gates to nil and bringing FPGA capabilities more in line with those of application-specific integrated circuits (ASIC).
This performance boost, combined with the empirical advantage of being software reprogrammable, has created a market shift towards FPGA-based designs for electronic devices. This shift was exemplified by the 2009 Gartner research report, which stated that for each new ASIC design, there are 30 being implemented with FPGAs.
The second trend is the increased availability and capability of high-level synthesis tools. Traditionally, hardware engineers have configured FPGA technology with programming tools geared towards embedded experts.
However, development environments such as NI LabVIEW FPGA can interpret intuitive, high-level graphical code and automatically generate the complex, low-level FPGA logic. This abstraction of complexity empowers engineers without digital hardware design expertise to create custom solutions using FPGAs.
For decades, the electronics industry has pursued its version of the Holy Grail – concurrent design and test. IP-to-the-pin, enabled by next-generation, reconfigurable instrumentation, is the catalyst we have been waiting for.
Dr. James Truchard, CEO and Co-founder of National Instruments recently commented: “The market shift to reconfigurable architectures will enable design and test engineers to operate at similar levels of abstraction. This is a key step to making concurrent system-level design and test a reality.” IP re-use, facilitated by IP-to-the-pin capability, shortens design verification/validation, improves production test and promotes profitability.
To learn more about IP-to-the-pin and other key trends in test for 2011, please visit ni.com/ato.
Richard Roberts is Technical Marketing Engineer, National Instruments UK and Ireland
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