Quick scan of past and future
14 January 2008
An overview of boundary-scan’s past, present and future, including the trends that are making this test technique increasingly popular
Boundary-scan it seems is now firmly back in the spotlight, just as it was 18 years ago when the IEEE std 1149.1 was first ratified and when Philips T&M (later to become JTAG Technologies) produced the industry’s first boundary-scan test program generator (BTPG) tool.
Shortly after the technology emerged, industry pundits predicted that JTAG/boundary-scan would solve all the test issues of the day and more: and we all ‘knew’ that In-Circuit Testers would soon be consigned to the tip. However, as we know now, the truth is a little different.
Sensible engineers are now talking about the ‘test mix’ and production/test professionals know that there is unlikely to be a single solution to their problems. Design for test guides and fault coverage reports are key elements of today’s test engineers’ tool-kits and must be used thoughtfully if the end result is to be near 100% test coverage.
Make no bones about it, JTAG was, and remains, a terrific idea. It is low-cost and offers tremendous potential for those working primarily in the digital and mixed-signal domains. It is the definitive BIST technique that can be used throughout a product life-cycle and in most instances costs little or nothing to add into a design.
JTAG can easily be adapted for system-level as well as board-level testing (essential in complex telecom and defence designs) and, when coupled with a functional test for example, boundary-scan can offer a potent overall test solution.
Since the standard’s inception, several enhancements have been made. For example, harmonisation in the way CPLDs and FPGAs are programmed ‘in-system’ (IEEE Std. 1532), at-speed testing of differential AC-coupled interconnects such as the LVDS structures seen in PCI-Express (IEEE Std. 1149.6), and even a standard aimed at testing analogue components (IEEE 1149.4) - described in some detail in the January 2006 edition of EM&T.
In step with these developments JTAG Technologies has continued to develop and supply novel tools and to support its burgeoning customer base, thought to be the largest in the world with approximately 5,000 systems shipped.
During the pioneering days of JTAG there was limited choice of suppliers, for boundary-scan tools were aimed primarily at large OEM organisations with budgets to match. Prices were easily several times higher in real terms and operation was often cumbersome. Today however design engineers can benefit from lower costs, better functionality and in most cases much improved ease-of use.
JTAG Technologies’ ProVision software, released in 2006, is just one example of the latest tools available which can benefit both the production test and design engineer alike. In ProVision’s case it can be used to generate structural board-level and system-level tests, create flash ISP algorithms and program CPLDs from a single user interface, utilising a reusable parts library that requires no scripting or coding.
Hardware too can now be delivered at an ‘everyman’ price. For example, JTAG Technologies’ recently released JT 3705/USB, a useful multiple TAP controller essential for maintaining signal integrity across large or diverse designs, costs only a few hundred pounds.
In addition to the classic testing of JTAG-to-JTAG device connections, memory block tests and so-called ‘cluster testing’ of non-JTAG parts has been much simplified with the introduction of re-usable cluster models and model maps. What’s more, fault coverage reports are generated in tandem with the project development and can be used to highlight parts of a circuit board or system that may require other, complementary test methods to be used (for example, flying-probe/ICT or functional test for assembled systems).
Early liaison between design and test will pay big dividends for both parties when assessing the best complementary techniques to be used on a given design. One simple method to assess the boundary-scan coverage of a design is by importing the fault coverage information from the developer tool into a graphical viewer system, such as ‘JTAG Visualizer’. Engineers from both disciplines can quickly gain an impression of the fault coverage of their design at either schematic or layout levels.
JTAG testing in 2008 is cheaper, faster and easier than it has ever been. As the market place has broadened (both for suppliers and target users), system start-up prices are now within much easier reach. Boundary-scan is now for the masses and no longer the chosen few.
Future developments in this arena will no doubt continue apace, and you will find active working groups looking into SJTAG (system-level JTAG) and IJTAG (internal JTAG IEEE P1687) for multi-board systems and IC-level testing respectively. Associated test standards are already underway – expect to see more on subjects such as SCITT (Static Component Interconnect Testing, a.k.a. IEEE P 1481) in the near future.
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