Trends in Test part 5 – Protocol aware test
09 June 2009
This is the final instalment in which National Instruments looks at trends in test, which this month focuses on protocol aware test.
We have previously looked at the explosion of wireless, easier access to FPGA-enabled instrumentation, and how software-defined instrumentation combined with off-the-shelf multicore technology is enabling us to push the boundaries of the systems we deploy.
Chip designers are facing a serious challenge; device complexity is advancing at an exponential rate, outstripping advances in test technology. By extension, the cost to manufacture complex semiconductor devices is decreasing significantly faster than the cost to test them.
Ultimately, as silicon-based devices begin to resemble complete systems, a higher level test methodology is required to handle tester complexity and reduce test development cost. This is exactly where protocol-aware ATE (Automated Test Equipment) fits in. Through the use of software-defined FPGA-based instrumentation, protocol-aware ATE can achieve intelligent, real-time communications via the standard pin-electronics found in traditional ATE.
This ever-increasing need for new test methodologies for the semiconductor industry is not surprising. Each decade sees semiconductor device complexity increase by a factor of ten, requiring a fundamental architectural shift in chip ATE. In the 1980s, chip tests made use of per pin timing; the 1990s incorporated mixed signal and memory tests; and the 2000s opened the door to integrated RF and serialiser/deserialiser testing.
Now, as we stride boldly towards the 2010s, the semiconductor chip industry needs to consider a new, smarter test architecture; protocol aware test. This architecture shares many similarities with the established hardware-in-the-loop (HIL) test methodology.
HIL test systems, which use simulations to emulate the native environment of the processor-based device under test (DUT), are already prevalent in the automotive and aerospace industries for validation tests on devices such as engine control units (ECUs). A specific example of hardware-in-the-loop tests is the verification of aircraft or missile autopilot systems. Testing such a system in its working environment is simply not practical; the autopilot systems must be verified long before they are installed in the aircraft. An HIL tester emulates the working environment of the embedded autopilot system, by deterministically simulating real world inputs and outputs. Therefore, the HIL simulation allows engineers to effectively validate their autopilot algorithms within a safe and controlled laboratory environment.
With the advent of complex Systems on a Chip (SoC), the semiconductor industry is demanding more stringent timing requirements than current testers can fulfil. Furthermore, the parallel digital lines which traditionally provided the interface to the SoCs are increasingly being replaced with high speed serial protocols, such as JTAG (Joint Test Action Group), SPI (Serial Peripheral Interface) or I2C (Inter-IC). Therefore, a higher level test methodology, such as protocol aware test, is required to reduce tester complexity and cost, while retaining the deterministic in situ tests provided by HIL simulations.
The concept of Protocol Aware ATE was originally raised at the 2007 International Test Conference (ITC) by Andrew Evans, a test engineer at Broadcom. It was a call to the test industry to consider the requirement of transactional level software so that design and test interact with the device at the same high level of abstraction.
In the case of microcontrollers or SoCs, where communication to the chip is through a protocol like SPI or I2C, the tester must be able to send and receive commands intelligently to the device, fulfilling the role of both a talker and a listener. The tester must dynamically make decisions based on the patterns it receives. This often requires hardware timing and ultra-low latency, ensuring that decisions are made within one timing cycle of the DUT. A technology that can meet these requirements and provide the foundation of protocol-aware ATE is the FPGA.
FPGAs are integrated circuits that incorporate a matrix of software configurable logic cells. This allows developers, who may not have a background in hardware design, to create sophisticated, bespoke circuitry.
Harnessing the power and flexibility of FPGA technology for protocol-aware ATE is something that was also noted in the Broadcom paper. Referring to the simulation of the DUT’s native environment, Evans stated: “Programmable logic would be used for the emulation. This logic would primarily consist of FPGAs and would reside between the ATE pin electronics and the rest of the ATE pin, which is the vector memory, pattern/timing generators, and formatters.”
Defining the functionality of the FPGA hardware involves coding and deploying algorithms written in HDL (hardware description language). Traditionally, the use of the FPGA platform has been limited to designers who have received HDL training and this has created somewhat of a barrier to many subject matter experts, such as academic scientists, test engineers and control experts. However, high-level graphical system design tools, like National Instruments’ LabVIEW FPGA, abstract many of the underlying complexities, opening the platform to a wider audience.
An additional benefit of the FPGA platform is that intellectual property (IP) used to implement the DUT can be leveraged in the test system design, reducing development time. In this way, protocol intelligence or awareness can be embedded behind each digital test pin, allowing ATE to become so much more than stored stimulus and response patterns.
FlexRIO, the latest FPGA-based product family from National Instruments is a new commercial off-the-shelf (COTS) platform ideal for protocol-aware test. FlexRIO provides flexible, reconfigurable I/O for high-performance instrumentation, along with an open customisable front end, which ensures that the exact connectivity and performance requirements of a test system can be met.
Ultimately, intelligent protocol-aware tests will make it much easier to interact with the devices during silicon bring-up and debug, allowing developers to feedback results from test into the design phase. FPGA will provide the foundation for this new test architecture, allowing the effective creation of custom hardware and the re-use of existing IP. This simplifies and accelerates the test development process, shortening both time to market and time to yield.
To read the previous instalments, use Linkcodes: 24588, 24069, 23276, and 22446.
Richard Roberts is Application Engineering Team Leader for National Instruments UK & Ireland
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