Maximising test coverage with boundary scan
05 July 2007
Boundary scan is still not the obvious option that it should be when deciding on a test strategy, argues Reg Waller, European Sales Director of ASSET InterTech
Achieving test coverage for every fault or defect that could possibly occur on a printed circuit board is certainly a lofty goal. Unfortunately, it is impossible to achieve because every contingency that might trigger a defect can never be reliably predicted. A more reasonable goal is to optimise test coverage to the highest degree possible – an open-ended objective with much room for interpretation.
Optimum coverage balances maximum test coverage with a number of tradeoffs. Usually cost is one of the primary tradeoffs. In addition, approaching maximum test coverage will necessitate the deployment of multiple test technologies, since each test technology or methodology has a finite limit on the coverage it can provide. Consequently, one of the first steps toward an optimised test plan for a particular PCB is to consider the various test technologies that are available.
Strengths and weaknesses
Each of the various test technologies that are prevalent today has its own strengths and weaknesses. For a host of reasons, boundary-scan or JTAG (as it is commonly referred to because development of the original specification (IEEE 1149.1) was initiated by the Joint Test Action Group) is moving to centre stage in more and more test plans these days.
In addition to boundary scan, today’s most popular test technologies include automatic optical inspection (AOI), automatic x-ray inspection (AXI), manual visual inspection (MVI), in-circuit test (ICT), manufacturing defect analysis (MDA), flying probe test (FPT) and processor emulation. Fortunately, several of these test technologies, such as boundary scan and ICT, or boundary scan and processor emulation can be combined on one test platform to reduce the number of separate test stations on a manufacturing line and to simplify test setup.
Because of its cost-effectiveness, PC-based boundary-scan test is taking on a greater role in the structural testing of PCBs. Boundary scan is relatively inexpensive, yet it offers very high structural test coverage where chips conforming to the IEEE 1149.1 standard are deployed. Boundary scan functions by stimulating and monitoring nets and connections on the PCB through chip-level registers (See Figure 1). As a result, boundary scan is one of the few non-intrusive test technologies. It requires no costly fixtures or on-board test points that eat up board space. And applying boundary scan tests places no added physical stress, which could disrupt solder joints, on the unit under test (UUT). With the right boundary-scan test system, test development can be highly automated and diagnostics can quickly isolate faults down to the level of an individual pin. The embedded boundary-scan infrastructure on a PCB can also facilitate on-board programming of memory devices or configuring programmable logic devices in-system. (See Figure 2 for a drawing of a typical PC-based boundary-scan test station.)
Moreover, the IEEE 1149.1 boundary-scan standard has been appropriated by several related test and programming standards as well as proposed standards that are still being developed. These include the relatively new IEEE 1149.6 standard for testing high-speed AC-coupled buses, the IEEE 1532 standard for concurrent programming of multiple devices, IEEE P1687, which is a preliminary standard for embedded test instrumentation, Intel™ IBIST for embedded self-test of high-speed buses, JEDEC’s STAPL standard for on-board programming, the System JTAG initiative and PICMG’s MicroTCA standard, which includes boundary scan as an optional test method.
All test technologies have their own strengths and weaknesses. ICT and MDA systems, for example, require test fixtures that are specific to each PCB they test. They also rely on spring-loaded probes for physical contact on test pads. The physical contact from the probes places stress on the UUT, which can jeopardise the less robust solder joints that have resulted from restrictions on solder compounds containing lead, like the RoHS requirements of the European Union. ICT can test for shorts and opens as well as perform analog measurements. Boundary scan tests can often be applied by ICT and MDA systems to increase the test coverage achieved on a single test platform.
Unlike the bed-of-nails fixtures of ICT and MDA, FPT systems have only a few physical probes on a test head which is moved to test pads on the UUT. The movement of the test head increases the time it takes to perform a FPT test. As a result, FPT is usually relegated to testing low-volume prototypes.
The visual inspection systems, AOI and AXI, do not electrically verify structural interconnects, but they can identify cracks in solder joints that may pass initial electrical tests. In addition, they can verify whether the correct device is in place, as well as is alignment and orientation. AXI has the added benefit of being able to inspect solder joints underneath devices like BGAs.
Optimising the test plan
Since no single test technology can come close to providing full test coverage, an optimised test plan will consist of the right combination of test methods that produces minimum test costs and maximum test coverage. (Figure 3). Once again, boundary scan comes to the forefront because it can increase test coverage at a cost level that is relatively low when compared to alternative test technologies such as ICT, MDA, FPT, AOI, AXI and others.
Besides cost considerations, some common misconceptions sometimes derail the development of a test plan with optimum test coverage. For example, some engineers may have the misconception that boundary scan is an inexpensive way of testing prototypes in design debug, but it is redundant to ICT in manufacturing test. The reality is that boundary scan and ICT complement one another quite effectively.
On densely populated PCBs with high-speed devices or devices in BGA packages, space for test pads may be hard to come by. Fortunately, many of these types of devices are prime candidates for boundary scan test since they usually conform to the boundary-scan standard. Boundary-scan tests developed for design debug purposes can migrate to production where they can be applied through the ICT system on the manufacturing line. Traditional ICT tests could be applied to other sections of the PCB that feature analogue devices or which have the space available for test pads. By combining boundary scan and ICT, the number of test probes on an ICT fixture can be reduced, making the fixture much simpler. This drives down fixture development and maintenance costs.
Similar to the relationship between boundary scan and ICT test, the give-and-take between structural test and functional test could also play a major role in the development of an optimized test plan. For example, the structural tests generated by boundary scan verify the quality of the assembly process by testing physical elements and their interconnections. Moreover, boundary scan can more effectively diagnose the root causes of faults than can functional test, which verifies that the PCB functions as intended.
Setting up a boundary-scan system for functional test purposes is often less expensive than the rack-and-stack set-ups, instrumentation and other technologies that are typically deployed in functional test. Other advantages of structural testing vis-à-vis functional test include faster test execution times, automatic test development techniques and the ability to quantify and compare expected test coverage metrics.
Real-world imperatives
Striving for optimum test coverage is not just a theoretical exercise. It is an imperative in today’s electronics industry because higher test coverage improves manufacturing yields and product quality, reduces product returns and enhances the marketplace competitiveness of the product. As the complexity, performance and functionality of chips and circuit board architectures such as high-speed serial buses continue their seemingly inexorable progress, cost-effective and non-intrusive structural test technologies like boundary scan will play a critical role in developing optimised test plans.
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